Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill

ABSTRACT

Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.16/578,647, filed Sep. 23, 2019, which is a continuation of U.S.application Ser. No. 16/002,843, filed Jun. 7, 2018, now U.S. Pat. No.10,424,495, which is a division of U.S. application Ser. No. 15/298,156,filed Oct. 19, 2016, now U.S. Pat. No. 10,008,395; each of which isincorporated herein by reference in its entirety.

TECHNICAL FIELD

The disclosed embodiments relate to semiconductor die assemblies. Inparticular, the present technology relates to stacked semiconductor dieassemblies with highly efficient thermal paths and a molded underfillmaterial, and associated systems and methods.

BACKGROUND

Packaged semiconductor dies, including memory chips, microprocessorchips, and imager chips, typically include a semiconductor die mountedon a substrate and encased in a plastic protective covering. The dieincludes functional features, such as memory cells, processor circuits,and imager devices, as well as bond pads electrically connected to thefunctional features. The bond pads can be electrically connected toterminals outside the protective covering to connect the die to higherlevel circuitry.

Semiconductor manufacturers strive to reduce the size of die packages tofit within the space constraints of electronic devices while increasingthe functional capacity of each package to meet operating parameters.One approach for increasing the processing power and/or storage capacityof a semiconductor package without substantially increasing the surfacearea covered by the package (i.e., the “footprint”) is to verticallystack multiple semiconductor dies on top of one another in a singlepackage. The dies in such vertically-stacked packages can beinterconnected by electrically coupling the bond pads of the individualdies with the bond pads of adjacent dies using through-silicon vias(TSVs). A Hybrid Memory Cube (HMC) is one particularly useful devicethat includes a plurality of memory dies stacked on the top of a logicdie.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view illustrating a semiconductor dieassembly in accordance with embodiments of the present technology.

FIG. 2A is a cross-sectional view and FIG. 2B is a top plan viewillustrating an aspect of a method of manufacturing a semiconductor dieassembly in accordance with embodiments of the technology.

FIG. 2C is a cross-sectional view and FIG. 2D is a top plan viewillustrating an aspect of a method of manufacturing a semiconductor dieassembly in accordance with embodiments of the technology.

FIG. 2E is a cross-sectional view and FIG. 2F is a top plan viewillustrating an aspect of a method of manufacturing a semiconductor dieassembly in accordance with embodiments of the technology.

FIG. 2G is a cross-sectional view and FIG. 2H is a top plan viewillustrating an aspect of a method of manufacturing a semiconductor dieassembly in accordance with embodiments of the technology.

FIG. 2I is a cross-sectional view illustrating an aspect of a method ofmanufacturing a semiconductor die assembly in accordance withembodiments of the technology.

FIG. 2J is a cross-sectional view illustrating an aspect of a method ofmanufacturing a semiconductor die assembly in accordance with thepresent technology.

FIG. 3 is a cross-sectional view illustrating a semiconductor dieassembly in accordance with an embodiment of the present technology.

FIG. 4 is a top plan view illustrating a semiconductor die assembly inaccordance with an embodiment of the technology.

FIG. 5 is a schematic view of a system that includes a semiconductor dieassembly configured in accordance with embodiments of the presenttechnology.

DETAILED DESCRIPTION

Specific details of several embodiments of stacked semiconductor dieassemblies with highly efficient thermal paths and molded underfillmaterial are described below along with the associated systems andmethods. The term “semiconductor die” generally refers to a die havingintegrated circuits or components, data storage elements, processingcomponents, and/or other features manufactured on semiconductorsubstrates. For example, semiconductor dies can include integratedmemory circuitry and/or logic circuitry. Semiconductor dies and/or otherfeatures in semiconductor die packages can be said to be in “thermalcontact” with one another if the two structures can exchange energythrough heat via, for example, conduction, convection and/or radiation.A person skilled in the relevant art will also understand that thetechnology may have additional embodiments, and that the technology maybe practiced without several of the details of the embodiments describedbelow with reference to FIGS. 1-5.

As used herein, the terms “vertical,” “lateral,” “upper” and “lower” canrefer to relative directions or positions of features in thesemiconductor die assemblies in view of the orientation shown in theFigures. For example, “upper” or “uppermost” can refer to a featurepositioned closer to the top of a page than another feature. Theseterms, however, should be construed broadly to include semiconductordevices having other orientations, such as inverted or inclinedorientations where top/bottom, over/under, above/below, up/down andleft/right can be interchanged depending on the orientation.

Stacked die arrangements, such as an HMC having a stack of a pluralityof memory dies attached to the top of a logic die, have severalmanufacturing challenges. For example, in vertically-stacked diepackages the heat from the individual dies is additive and theaggregated heat is difficult to dissipate. This increases the operatingtemperatures of the individual dies, the junctions between the dies, andthe package as a whole, which can cause the stacked dies to reachtemperatures above their maximum operating temperatures (T(max)). Theproblem is also exacerbated as the density of the dies in the packageincreases. Moreover, when there are different types of dies in the diestack, the T(max) of the whole device is limited to the T(max) of thedie with the lowest T(max).

Another challenge of stacked die assemblies is that packaging capable ofdissipating sufficient heat from the dies is expensive to manufacture.Many existing designs initially flow a liquid dispense underfillmaterial between the dies and then cover the die stack with a thermallyconductive “lid” that completely encloses the top and sides of thememory die stack. This process, however, constitutes a considerableportion of the overall cost of the finished device.

To address these challenges, one embodiment of the present technology isa semiconductor die assembly comprising a package support substrate, afirst semiconductor die mounted to the package support substrate, and adie stack including a plurality of second semiconductor dies stacked oneach other. The first semiconductor die has a stacking site and alateral region extending laterally from the stacking site. The die stackhas a bottom second semiconductor die mounted to the stacking site ofthe first semiconductor die, a top second semiconductor die having a topsurface defining a top surface area of the die stack, and sides. Thesemiconductor die assembly further includes a thermal transfer structureattached to the lateral region of the first semiconductor die, and thethermal transfer structure surrounds the die stack. The thermal transferstructure has a cavity in which the second semiconductor dies arepositioned and an opening larger than the top surface area of the diestack. The semiconductor die assembly further comprises a moldedunderfill material in the cavity between the second semiconductor diesand the thermal transfer structure. The underfill material covers thesides of the die stack.

Another embodiment of the present technology is a semiconductor dieassembly comprising a package support substrate, a first semiconductordie mounted to the package support substrate, and a die stack having aplurality of second semiconductor dies. The first semiconductor die hasa lateral region and a stacking area inward of the lateral region, andthe die stack includes a bottom second semiconductor die mounted to thestacking area of the first die and a top second semiconductor die havinga top surface. The semiconductor die assembly of this embodiment alsoincludes a thermally conductive frame around the die stack, and aninjected underfill material between the thermally conductive frame andthe die stack. The thermally conductive frame has a bottom surfacemounted to the lateral region of the first semiconductor die and anupper surface at an elevation that is at or above the top surface of thetop second die. The injected underfill material has a height at leastcoplanar with the upper surface of the thermally conductive frame. Insome embodiments, the injected underfill material can cover the topsurface of the top second semiconductor die.

FIG. 1 is a cross-sectional view illustrating a semiconductor dieassembly 100 (“assembly 100”) in accordance with an embodiment of thepresent technology. The assembly 100 includes a package supportsubstrate 102, a first semiconductor die 110 mounted to the packagesupport substrate 102, and a plurality of second semiconductor dies 120arranged in a stack 122 at a stacking area 111 of the first die 110,such as a central region or an off-center region. The first die 110further includes at least one lateral region 112 laterally outboard ofthe second dies 120 on at least one side of the first die 110. In theembodiment shown in FIG. 1, the first die 110 has two lateral regions112 outboard of opposing sides of the die stack 122. The die stack 122can include a bottom second die 120 a mounted to the first die 110 and atop second die 120 b having a top surface 124. The top surface 124defines a top surface area of the die stack 122 at an elevation E1.

The assembly 100 can further include a thermal transfer structure (TTS)130 around the die stack 122. In the embodiment illustrated in FIG. 1,the TTS 130 is a frame having a bottom surface 132 adhered to thelateral portions 112 of the first die 110 and the support substrate 102by an adhesive 133, an upper surface 134 at an elevation E2, and aninner sidewall 136. The elevation E2 of the upper surface 134 is abovethe elevation E1 of the top surface 124 of the top second die 120 b inthe illustrated example. In other embodiments, the upper surface 134 canbe at least substantially coplanar with the top surface 124. The innersidewall 136 defines a cavity 138 in which the second dies 120 arepositioned and an opening defined by the upper edge 139 where thesidewall 136 meets the upper surface 134. The opening shown in FIG. 1 islarger than the top surface area of the top surface 124. The TTS 130 ismade from a material with high thermal conductivity, such as copper,aluminum, silicon, or other suitable thermally conductive materials. Inseveral embodiments the TTS 130 also has a coefficient of thermalexpansion (CTE) similar to the CTE of the substrate material of thefirst die 110 to reduce stress on the dies 110/120 caused duringtemperature cycling in normal use while still having a high thermalconductivity to effectively transfer heat from the first die 110. Thisis expected the mitigate cracks in the dies 110/120 or delamination ofthe TTS 130. Suitable CTE-matching materials for the TTS 130 include,but are not limited to, molybdenum (Mo), alloys of copper-tungsten(Cu—W), alloys of copper-molybdenum (Cu—Mo), silicon carbide (SiC)and/or aluminum nitride (AlN). In some instances, these materials mayalso be lighter than copper and result in significantly lighterpackages. When the TTS 130 is made from a metal, it can be stamped orlaser cut into a suitable shape to form the opening and surround thesecond dies 120 of the die stack 122. The adhesive 133 can be a thermalinterface material (“TIM”) or another suitable adhesive. For example,TIMs and other adhesives can include silicone-based greases, gels, oradhesives that are doped with conductive materials (e.g., carbonnano-tubes, solder materials, diamond-like carbon (DLC), etc.), as wellas phase-change materials.

The assembly 100 further includes an underfill material 160 (individualportions identified respectively by reference numbers 160 a and 160 b)between each of the second dies 120 and between the first die 110 andthe bottom second die 120 a. The embodiment of the underfill material160 shown in FIG. 1 has a side underfill portion 160 a extending orotherwise covering the sides of the die stack 122, and a top underfillportion 160 b over the top surface 124 of the top second die 120 b. Thetop underfill portion 160 b can directly contact the top surface 124 ofthe top second die 120 b.

The assembly 100 can optionally include a thermally conductive lid 170adhered to the upper surface 134 of the TTS 130 and the top underfillportion 160 b by an adhesive 172. The conductive lid 170 can be a platemade from a material having a high thermal conductivity, such as copper,aluminum, silicon, or other suitable materials.

The assembly 100 is expected to provide enhanced thermal dissipation ofheat from the first die 110 and the stack 122 of second dies 120. Forexample, since the TTS 130 is made from a material with a high thermalconductivity and directly mounted on the lateral regions 112 of thefirst die 110 via a TIM, it efficiently transfers heat along a pathdirectly from the lateral region 112 of the first die 110 to the thermallid 170. The TTS 130 is also simple and easy to install, so it providesa simple, cost-effective way to efficiently dissipate heat from the hightemperature lateral portions 112 of the first die 110. Moreover, it isalso easy to injection mold the underfill material 160 into the cavity138 because the large opening in the TTS 130 enables a simple injectionmold platen to be placed directly on the TTS 130.

Several embodiments of the assembly 100 shown in FIG. 1 can accordinglyreduce the operating temperatures of the individual dies 110, 120 in theassembly 100 such that they stay below their designated maximumtemperatures (Tmax). This can be very useful when the assembly 100 isarranged as an HMC because the first die 110 is generally a larger logicdie and the second dies 120 are generally memory dies, and logic diestypically operate at a much higher power level than memory dies (e.g.,5.24 W compared to 0.628 W). The logic die HMC configuration generallyconcentrates a significant amount of heat at the lateral regions 112 ofthe first die 110. The logic die may also have a higher power density atthe lateral regions 112, which further concentrates heat and therebyproduces higher temperatures in the lateral regions 112. As such, bydirectly coupling a large percentage of the lateral regions 112 of thefirst die 110 to the highly conductive TTS 130 via the adhesive 133, theheat can be efficiently removed from the lateral regions 112 of thefirst die.

FIGS. 2A-2J illustrate sequential aspects of a method of manufacturingthe assembly 100 in accordance with embodiments of the presenttechnology. FIG. 2A is a cross-sectional view and FIG. 2B is a top planview of the assembly 100 before the TTS and underfill material have beeninstalled. Referring to FIG. 2A, the package support substrate 102 isconfigured to connect the first and second dies 110, 120 to externalelectrical components of higher-level packaging (not shown). Forexample, the package support substrate 102 can be an interposer orprinted circuit board that includes semiconductor components (e.g.,doped silicon wafers or gallium arsenide wafers), non-conductivecomponents (e.g., various ceramic substrates, such as aluminum oxide(Al2O3), aluminum nitride (AlN), etc.), and/or conductive portions(e.g., interconnecting circuitry, TSVs, etc.). In the embodimentillustrated in FIG. 2A, the package support substrate 102 iselectrically coupled to the first die 110 at a first side 103 a of thepackage support substrate 102 via a plurality of first electricalconnectors 104 a and to external circuitry (not shown) at a second side103 b of the package support substrate 102 via a plurality of secondelectrical connectors 104 b (collectively referred to as “the electricalconnectors 104”). The electrical connectors 104 can be solder balls,conductive bumps and pillars, conductive epoxies, and/or other suitableelectrically conductive elements. In various embodiments, the packagesupport substrate 102 can be made from a material with a relatively highthermal conductivity to enhance heat dissipation at the back side of thefirst semiconductor die 110.

As shown in FIGS. 2A and 2B, the first die 110 can have a largerfootprint than the stacked second dies 120. The first and second dies110, 120 can be rectangular, circular, and/or other suitable shapes andmay have various different dimensions. Referring to FIG. 2B, forexample, the first die 110 can have a length L1 and a width W1, and theindividual second dies 120 can each have a length L2 and a width W2.Each lateral region 112 (known to those skilled in the art as a “porch”or “shelf”) of the first die 110 can be defined by the relativedimensions of the first and second dies 110 and 120 and the position ofthe die stack 122 on a forward-facing surface 114 (FIG. 2A) of the firstdie 110. In the embodiment illustrated in FIGS. 2A and 2B, the die stack122 is centered with respect to the width W1 of the first die 110 suchthat lateral regions 112 extend laterally beyond two opposite sides ofthe stack 122 by equal distances. In embodiments where both the widthand length of the first die 110 are greater than those of the centereddie stack 122, a continuous lateral region 112 may extend around theentire perimeter of the second dies 120. In other embodiments, the stack122 may be offset with respect to the forward-facing surface 114 (FIG.2A) of the first die 110 such that only one lateral region 112 extendsoutboard from only one side of the stack 122. In further embodiments,the first and second dies 110 and 120 can be circular, and therefore therelative diameters of the first and second dies 110 and 120 define thelateral region 112.

The first and second dies 110, 120 can include various types ofsemiconductor components and functional features, such as dynamicrandom-access memory (DRAM), static random-access memory (SRAM), flashmemory, other forms of integrated circuit memory, processing circuits,imaging components, and/or other semiconductor features. In variousembodiments, for example, the assembly 100 is configured as an HMC inwhich the stacked second dies 120 are memory dies that provide datastorage and the first die 110 is a high-speed logic die that providesmemory control (e.g., DRAM control) within the HMC. In otherembodiments, the first and second dies 110 and 120 may include othersemiconductor components, and/or the semiconductor components of theindividual second dies 120 in the stack 122 may differ.

As shown in FIG. 2A, the second dies 120 can be electrically coupled toone another in the stack 122 and to the underlying first die 110 by aplurality of electrically conductive elements 125 positioned betweenadjacent dies 110, 120. Although the stack 122 shown in FIG. 2A includeseight second dies 120 electrically coupled together, in otherembodiments the stack 122 can include more or less than eight dies(e.g., 2-4 dies, or at least 9 dies etc.). The electrically conductiveelements 125 can have various suitable structures, such as pillars,columns, studs, bumps, and can be made from copper, nickel, solder(e.g., SnAg-based solder), conductor-filled epoxy, and/or otherelectrically conductive materials. In selected embodiments, for example,the electrically conductive elements 125 can be copper pillars, whereasin other embodiments the electrically conductive elements 125 caninclude more complex structures, such as bump-on-nitride structures.

As further shown in FIG. 2A, the individual second dies 120 can eachinclude a plurality of TSVs 126 aligned on one or both sides withcorresponding electrically conductive elements 125 to provide electricalconnections at opposing sides of the second dies 120. Each TSV 126 caninclude an electrically conductive material (e.g., copper) that passescompletely through the individual second dies 120 and an electricallyinsulative material surrounding the electrically conductive material toelectrically isolate the TSVs 126 from the remainder of the second dies120. Though not shown in FIG. 2A, the first die 110 can also include aplurality of TSVs to electrically couple the first die 110 to higherlevel circuitry. Beyond electrical communication, the TSVs 126 and theelectrically conductive elements 125 provide thermal conduits throughwhich heat can be transferred away from the first and second dies 110and 120. In some embodiments, the dimensions of the electricallyconductive elements 125 and/or the TSVs 126 can be increased to enhanceheat transfer vertically through the stack 122. For example, theindividual electrically conductive elements 125 can each have a diameterof about 15-30 μm or other suitable dimensions to enhance the thermalpathway through the dies 110, 120. In other embodiments, the second dies120 can be electrically coupled to one another and to the first die 110using other types of electrical connectors (e.g., wirebonds) that mayalso provide thermal pathways through the stack 122.

In various embodiments, the assembly 100 optionally includes a pluralityof thermally conductive elements 128 (shown in broken lines) positionedinterstitially between the electrically conductive elements 125. Theindividual thermally conductive elements 128 can be at least generallysimilar in structure and composition as that of the electricallyconductive elements 125 (e.g., copper pillars). However, the thermallyconductive elements 128 are not electrically coupled to the TSVs 126 orother electrically active components of the dies 110 and 120, andtherefore the thermally conductive elements 128 do not provideelectrical connections between the second dies 120. Instead, thethermally conductive elements 128 are electrically isolated “dumbelements” that increase the overall thermal conductivity through thestack 122 to enhance the heat transfer upward through the die stack 122.For example, in embodiments where the assembly 100 is configured as aHMC, the addition of the thermally conductive elements 128 between theelectrically conductive elements 125 has been shown to decrease theoperating temperature of the HMC by several degrees (e.g., about 6-7°C.).

FIG. 2C is a cross-sectional view and FIG. 2D is a top plan viewillustrating the assembly 100 after the TTS 130 has been attached to thefirst die 110 and the package support substrate 102. Referring to FIG.2C, an inner portion of the TTS 130 is configured to be positioned overthe lateral regions 112 of the first die 110. The sidewall 136 of theTTS 130 extends to a height (H1) relative to the stack 122 of seconddies 120 that is at or above the elevation of the top surface 124 of thetop second die 120 b. The sidewall 136 is also spaced apart from thestack 122 of second dies 120 by a gap (G) such that the TTS 130 covers asignificant percentage of the lateral region 112 and the opening definedby the edge 139 is larger than the surface area of the top surface 124of the top second die 120 b. The adhesive 133 can be a TIM. In theembodiment shown in FIG. 2D, the TTS 130 is a frame or a ring thatcompletely surrounds the second dies 120 and exposes the top surface 124of the top second die 120 b.

FIG. 2E is a cross-sectional view illustrating another stage of themethod of manufacturing the assembly 100 after a mold platen 210 isplaced against the upper surface 134 of the TTS 130, and FIG. 2F is atop view of the mold platen 210 over the first die 110, the die stack120, and the TTS 130. The mold platen has an inlet 212 through which anunderfill material can be injected under pressure into the cavity 138(FIG. 2E) defined by the TTS 130. The mold platen 210 can also include avent 214 (FIG. 2F) at an opposing side of the die stack 122 relative tothe inlet 212.

FIG. 2G is a cross-sectional view illustrating the assembly 100 as theunderfill material 160 is injected through the inlet 212 and into thecavity 138. The underfill material 160 flows over the top surface 124 ofthe top second die 120 b and along the sides of the die stack 122 untilthe underfill material 160 is between: (a) each of the second dies 120;(b) the first die 110 and the bottom second die 120 a; and (c) the sidesof the die stack 122 and the inner sidewall 136 of the TTS 130. Theunderfill material 160 is typically an injectable molded underfillmaterial.

FIG. 2H is a top plan view illustrating the method at the stage of FIG.2G. As shown in FIG. 2H, the molded underfill material 160 flows acrossthe top surface of the top second die 120 b (arrow F) because the moldplaten 210 is spaced apart from the top surface of the top second die120 b. The molded underfill material 160 accordingly has a leading edge162 that propagates along the top surface of the top second die 120 b.As the molded underfill material 160 fills the cavity 138 (FIG. 2G), airdisplaced from the cavity 138 flows out of the vent 214.

FIG. 2I is a cross-sectional view illustrating the assembly 100 afterthe underfill material 160 has been injected into the cavity until itreaches the bottom of the mold platen 210. As a result, the bottomsurface of the mold platen 210 can define the top surface of theunderfill material in several embodiments. In other embodiments, thebottom surface of the mold platen 210 can be formed to create thedesired height of the top surface of the underfill material 160 eitherat, below or above the elevation of the upper surface 134 of the TTS130.

FIG. 2J is a cross-sectional view illustrating the assembly 100 afterthe mold platen 210 has been removed. The top underfill portion 160 baccordingly covers the top surface 124 of the top second die 120 b, andthe top surface of the top underfill portion 160 b is at leastsubstantially coplanar with the upper surface 134 of the TTS 130. Theside underfill portion 160 a completely covers the sides of all thesecond dies in the die stack 122 and fills the remainder of the cavity138 including the interstitial spaces between the second dies 120 andthe space between the first die 110 and the bottom second die 120 a. Athermally conductive lid, such as the thermally conductive lid 170 shownin FIG. 1, can optionally be attached to the upper surface 134 of theTTS 130 and the top surface 163 of the top underfill portion 160 b usingan adhesive (e.g., a TIM).

The process of manufacturing the assembly 100 illustrated in FIGS. 2A-2Jis expected to economically produce a packaged hybrid semiconductordevice with high thermal conductivity to efficiently dissipate heatgenerated by the first die 110. Instead of conventional lids thatcompletely encase the sides and cover the top of the die stack of seconddies, the TTS 130 of the assembly 100 is inexpensive to manufacture,enables easy injection molding of the underfill material 160 directlythrough the reusable mold platen 210, and is easy to install. This isexpected to reduce the cost of manufacturing packaged hybridsemiconductor devices. Additionally, because the TTS 130 is adhered tothe lateral region 112 of the first die 110 via a thermally conductiveadhesive before the underfill material 160 is injected into the cavity138, the TTS 130 is able to contact a large percentage of the lateralregion 112 of the first die 110. This is expected to further enhance thethermal efficiency of the removal of heat from the first die 110.

FIG. 3 is a cross-section view of a semiconductor die assembly 300 inaccordance with another embodiment of the present technology. Likereference numbers refer to like components in FIGS. 1 and 3. Thedifference between the assembly 100 and the assembly 300 is that theupper surface 134 of the TTS 130 of the assembly 300 is coplanar withthe top surface 124 of the top second die 120 b. As a result, the moldedunderfill material 160 completely covers the sides of the die stack 122but not the top surface 124 of the top second die 120 b. The lack of amold cap over the top surface 124 of the top second die 120 b enablesthe thermally conductive lid 170 to be adhered directly to the topsurface 124 of the top second die 120 b by the adhesive 172. The processof manufacturing the assembly 300 is similar to that described abovewith respect to the assembly 100 in FIGS. 2A-2J, but the mold platen canrest directly on the upper surface 134 of the TTS 130 and the topsurface 124 of the top second die 120 b during the injection moldingprocess, or a thin removable protective film can be between the moldplaten 210 and the TTS 130 and top surface 124 of the top second die 120b. The underfill material 160 is accordingly limited to flowing aroundthe sides of the die stack 122. As a result, the assembly 300 enhancesthe heat transfer from the die stack 122 directly to the central portionof the thermally conductive lid 170.

FIG. 4 is a top plan view of an aspect of manufacturing a semiconductordie assembly 400 that is similar to the semiconductor die assemblies 100and 300 described above. In this embodiment, a mold platen 410 has aninlet 412 at one and but no vents at the other end. Instead of providinga vent through the mold platen 410, the adhesive 133 that attaches theTTS 130 to the first die 110 has vent channels 414 at one end of thedevice. The underfill material can accordingly flow through the cavitydefined by the TTS 130 as described above with reference to FIGS. 2G, 2Hand 3, but the air is displaced from the cavity through the ventchannels 414 in the adhesive 133.

Any one of the stacked semiconductor die assemblies described above withreference to FIGS. 1-4 can be incorporated into any of a myriad oflarger and/or more complex systems, a representative example of which issystem 500 shown schematically in FIG. 5. The system 500 can include asemiconductor die assembly 510, a power source 520, a driver 530, aprocessor 540, and/or other subsystems or components 550. Thesemiconductor die assembly 510 can include features generally similar tothose of the stacked semiconductor die assemblies described above, andcan therefore include multiple thermal paths with good coverage of thelateral region 112 of the first die 110 that enhance heat dissipation.The resulting system 500 can perform any of a wide variety of functions,such as memory storage, data processing, and/or other suitablefunctions. Accordingly, representative systems 500 can include, withoutlimitation, hand-held devices (e.g., mobile phones, tablets, digitalreaders, and digital audio players), computers, and appliances.Components of the system 500 may be housed in a single unit ordistributed over multiple, interconnected units (e.g., through acommunications network). The components of the system 500 can alsoinclude remote devices and any of a wide variety of computer readablemedia.

From the foregoing, it will be appreciated that specific embodiments ofthe technology have been described herein for purposes of illustration,but that various modifications may be made without deviating from thedisclosure. For example, although many of the embodiments of thesemiconductor dies assemblies are described with respect to HMCs, inother embodiments the semiconductor die assemblies can be configured asother memory devices or other types of stacked die assemblies. Inaddition, the semiconductor die assemblies illustrated in FIGS. 1-5 havea plurality of second semiconductor dies arranged in a stack on thefirst semiconductor die, but other embodiments can have one firstsemiconductor die stacked on one or more of the second semiconductordies. Certain aspects of the new technology described in the context ofparticular embodiments may also be combined or eliminated in otherembodiments. Moreover, although advantages associated with certainembodiments of the new technology have been described in the context ofthose embodiments, other embodiments may also exhibit such advantagesand not all embodiments need necessarily exhibit such advantages to fallwithin the scope of the technology. Accordingly, the disclosure andassociated technology can encompass other embodiments not expresslyshown or described herein.

We claim:
 1. A semiconductor die assembly, comprising: a firstsemiconductor die having a central region and a lateral region; a diestack having one or more second semiconductor dies carried by thecentral region of the first semiconductor die; an adhesive over at leasta portion of the outer region of the first die, wherein the adhesiveincludes a vent channel extending from an external surface of theadhesive to an internal surface adjacent the die stack; a heat transferstructure at least partially carried by the lateral region of the firstsemiconductor die; and an underfill material between the heat transferstructure and the die stack.
 2. The semiconductor die assembly of claim1 wherein the heat transfer structure includes a planar lower surfaceattached to the adhesive.
 3. The semiconductor die assembly of claim 1wherein the die stack has a first longitudinal side and a secondlongitudinal side, and wherein the vent channel extends from theexternal surface of the adhesive to the internal surface adjacent thefirst longitudinal side.
 4. The semiconductor die assembly of claim 3wherein the heat transfer structure has a sidewall spaced apart from thefirst and second longitudinal sides of the die stack by a gap.
 5. Thesemiconductor die assembly of claim 1 further comprising a lid carriedby the heat transfer structure above the die stack.
 6. The semiconductordie assembly of claim 1, further comprising a package support substrate,wherein: the first semiconductor die is mounted to an upper surface thepackage support substrate; the adhesive includes a first portion overthe lateral region of the first semiconductor die and a second portionover the package substrate; and the heat transfer structure is at leastpartially carried by the package substrate.
 7. The semiconductor dieassembly of claim 6 wherein the package support substrate includes alower surface having a plurality of electrical connectors, and whereinthe first semiconductor die is electrically coupled the plurality ofelectrical connectors.
 8. The semiconductor die assembly of claim 1wherein an upper die of the die stack has a top surface area, andwherein the heat transfer structure has an opening larger than the topsurface area of the upper die.
 9. A semiconductor die assembly,comprising: a package substrate having a first surface and a secondsurface opposite the first surface; a first die carried by the firstsurface of the package substrate, the first die having a stacking regionand a lateral region outboard of the stacking region; a die stack havingone or more second dies carried by the stacking region, the die stackinghaving an uppermost surface with a surface area; a thermal transferstructure attached to the lateral region of the first die and thepackage substrate, wherein the thermal transfer structure has an openinglarger than the surface area of the uppermost surface; and an underfillmaterial between the thermal transfer structure and the die stack, theunderfill material covering sides of the die stack up to at least theuppermost surface of the die stack.
 10. The semiconductor die assemblyof claim 9 wherein the thermal transfer structure extends to a heightabove an elevation of the uppermost surface of the die stack.
 11. Thesemiconductor die assembly of claim 9 wherein the thermal transferstructure includes a sidewall defining a cavity, and wherein the diestack is positioned in the cavity.
 12. The semiconductor die assembly ofclaim 11 wherein the die stack includes two or more second dies, andwherein the die stack includes thermally conductive elements positionedbetween and electrically isolated from each of the two or more seconddies.
 13. The semiconductor die assembly of claim 9 wherein the thermaltransfer structure includes a planar lower surface attached to thelateral region of the first die and the package substrate by acontinuous adhesive.
 14. The semiconductor die assembly of claim 9,further comprising an adhesive attaching the thermal transfer structureto the lateral region of the first die and the package substrate,wherein the adhesive includes a vent channel extending from an externalsidewall of the adhesive to an internal sidewall.
 15. The semiconductordie assembly of claim 9, further comprising a lid at least partiallycarried by the thermal transfer structure.
 16. The semiconductor dieassembly of claim 15 wherein the lid is at least partially carried bythe uppermost surface of the die stack.
 17. The semiconductor dieassembly of claim 9 wherein the die stack is electrically coupled to thefirst die via one or more conductive elements positioned between the diestack and the first semiconductor die.
 18. The semiconductor dieassembly of claim 9 wherein the die stack includes two or more seconddies, wherein each of the two or more second dies in the die stack isseparated by a space, and wherein the underfill material fills the spacebetween each of the two or more second dies in the die stack.
 19. Astacked semiconductor die assembly, comprising: a first die having anupper surface with a central portion and a peripheral region outboard ofthe central region; a die stack having one or more second dies carriedby the central region of the upper surface of the first die; a thermallyconductive frame attached to the lateral region of the upper surface ofthe first die, wherein the thermally conductive frame includes a cavityhaving a longitudinal footprint larger than the die stack, and whereinthe thermal; and an underfill material filling the cavity to anelevation at or above an upper surface of the die stack.
 20. The stackedsemiconductor die assembly of claim 19 further comprising an adhesiveattaching the thermally conductive frame to the peripheral region of thefirst die, wherein the adhesive includes a vent channel extending froman external sidewall of the adhesive to an internal sidewall.